- Control Unit
- Arithmetic Logic Unit
- Dedicated registers
- Buses
- Uses control signals to enable data to be read from/ written to memory
- It decodes every instruction that the processor will execute to know what needs to be done
A communication system that transfers data between components, components are connecteb using buses
- A set of parallel instructions that allow internal components to communicate with each other and exchange data, it connect the CPU, main memory and I/O controllers
Made of:
- Address bus
- Data bus
- Control bus
External buses - used to connect peripherals to the processor. Either series or parallel
The control and data bus are bidirectional, so data can be both written to/read from a memory location
- Send control signals between internal and external components (bidirectional)
- Memory read - Places data from a certain memory location onto the data bus
- Memory write - Stores data from the data bus onto a certain memory location
- Bus request - Signifies that a component needs to access a bus
- Interrupt request - Signifies that an error or exception has occurred that requires the attention of the CPU
- Clock signals - The control bus supplies the components with clock pulses generated by the system clock
The address must be on the data bus
Transfers data/instructions between components (bidirectional)
Width refers to the no of parallel lines, this the determines the no of bits that can be transferred
- Transmits memory addresses specifying where data should be sent/retrieved from
Words(16, 32 or 64 bits)
Performs arithmetic, logical and shift operations on data
Stores results from the ALU
PC - Holds the memory address of the next instruction to be executed
CIR - Holds the address in memory which is split into opcode and operand
MAR - Holds the address in memory that is meant to be read from/written to
MDR - Temporarily holds data that has been read or that needs to be written to
Accumulator - Holds the results of an instruction
- The address of the next instruction is copied from
the PC to the MAR
- The instruction held at the MAR is then sent to RAM via the address bus & waits for a control signal to know what needs to be done
- The control unit sends a control signal to RAM
- This now allows the data to be sent to the MDR from RAM through the data bus
- The data is then copied from the MDR to the CIR
- Finally the contents of the PC are incremented
- The instruction in the CIR is decoded
- It's then split into operand and opcode to determine the type of instruction it is
- It's then passed on to the accumulator
- The opcode is executed on the operand
- Cache size - Larger the cache, the more frequently used data it can store
- No of cores - The more cores, the more instructions the computer can execute at the same time(Not all programs can utilise this as they haven't been designed to do so)
- Clock speed - The greater the clock speed, the faster instructions can be carried out
The process of carrying out multiple instructions concurrently
- A control unit
- An ALU
- Special registers
- RAM
Reduces the chances of a bottleneck occuring
- It simplifies the design of the control unit and is cheaper to develop
- Programs can be optimised to use less memory. This can be done by reusing code, loops & branches.
Keeps data/instruction in separate memory units
- Instructions are exectued quicker as they're fetched in parallel
- Instructions/Data are held in separate memory units which have different word lengths, which can make more efficient use of space
L1 cache - Has very fast memory cells, but a small capacity
L2 cache - Has relatively fast memory cells, with a medium sized capacity
L3 cache - Has a large capacity, but slow memory cells
They're a combination of von neumann and harvard architectures
The von neumann architecture works on the data/instruction in main memory, & the harvard architecture divides cache into instruction cache and data cache