SPI review
Which type of peripheral often uses SPI for high-speed data transfer?
SD card modules.
Is SPI a full-duplex, half-duplex, or simplex communication protocol?
Full-duplex
What component is essential for serial-to-parallel conversion in SPI?
A shift register device.
Which pin is used for data output from the Master?
MOSI (Master Out Slave In).
Does SPI require an address for each slave device like I2C?
No
For SPI Mode 0, what are the values of CPOL and CPHA?
CPOL=0, CPHA=0.
What is the main disadvantage of SPI compared to I2C for multiple slaves?
Requires a dedicated Slave Select pin for each slave on the master.
Is SPI typically used for on-board communication or inter-board communication?
On-board communication
What happens to data on the MISO line if a Slave is not selected?
It enters a high-impedance state.
Can SPI communicate over long distances reliably without special hardware?
No
Which pin allows the Slave to send data to the Master?
MISO (Master In Slave Out).
How many unique SPI modes are defined by combinations of CPOL and CPHA?
Four
If CPOL is 1, what is the idle state of the SCK line?
It maintains a high logic level.
What does CPOL determine in SPI?
The idle state of the SCK line.
Role of SCK in SPI communication.
Clock signal for synchronization.
Which of these protocols is NOT a common alternative to SPI for short-distance communication?
CAN bus (Controller Area Network).
How many wires minimum does a basic SPI communication require (excluding power/ground)?
Four wire connection path.
Which data ordering is common for SPI communication?
Both LSB first and MSB first.
What is a key advantage of SPI over I2C regarding speed?
It does not have slave addressing overhead.
What is the primary role of the SS (Slave Select) pin?
To enable or disable a specific slave device.
In a multi-slave configuration, how many SS lines are typically needed from the Master if there are 'N' slaves?
N
What type of communication is SPI (synchronous/asynchronous)?
Synchronous
Does SPI have built-in acknowledgement or error-checking mechanisms?
No
What does CPHA determine in SPI?
The sampling edge of the clock signal.
Can a single SPI bus have multiple Masters?
No